Shibata, Nobutaro: search on Z-Library

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1

An STM-16 Frame Termination VLSI With 2.5-Gb/s/Pin Input/Output Buffers: High-Speed and Low-Power Multi- $\mathrm{V}_{\rm DD}$ CMOS/SIMOX Techniques

Shibata, Nobutaro, Ohtomo, Yusuke, Nishisaka, Mika, Sato, Yasuhiro

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 6.05 MB

english, 2015

2

Size-configurable 200-MHz low-power SRAM macrocells for MPEG2 video-encoding LSIs: Performance enhancement with embedded registers

Nobutaro Shibata, Hiroki Morimura

Journal:

Electronics and Communications in Japan (Part II: Electronics))

Year:

1999

Language:

english

File:

PDF, 1001 KB

english, 1999

3

A size-configurable two-port SRAM macrocell with power reduction architecture using a writing-enable signal

Nobutaro Shibata, Hisayo Katoh

Journal:

Electronics and Communications in Japan (Part II: Electronics))

Year:

1999

Language:

english

File:

PDF, 316 KB

english, 1999

4

A SOI Multi-VDD Dual-Port SRAM Macro for Serial Access Applications

SHIBATA, Nobutaro, WATANABE, Mayumi, ISHIHARA, Takako

Journal:

IEICE Transactions on Electronics

Year:

2017

Language:

english

File:

PDF, 1.03 MB

english, 2017

5

Signal-to-Noise Ratio Analysis of a Noisy-Channel Model for a Capacitively Coupled Personal Area Network

Sasaki, Ai-ichiro, Ishihara, Takako, Shibata, Nobutaro, Kawano, Ryusuke, Morimura, Hiroki, Shinagawa, Mitsuru

Journal:

IEEE Transactions on Antennas and Propagation

Year:

2013

Language:

english

File:

PDF, 3.51 MB

english, 2013

6

Memory macrocell techniques for 1-V battery-operated ASICs

Nobutaro Shibata, Shigeru Date

Journal:

Electronics and Communications in Japan (Part II: Electronics))

Year:

1996

Language:

english

File:

PDF, 900 KB

english, 1996

7

Fast ROM macrocells for ASICs

Nobutaro Shibata

Journal:

Electronics and Communications in Japan (Part II: Electronics))

Year:

1996

Language:

english

File:

PDF, 855 KB

english, 1996

8

High-Density RAM/ROM Macros Using CMOS Gate-Array Base Cells: Hierarchical Verification Technique for Reducing Design Cost

Shibata, Nobutaro, Gotoh, Yoshinori

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 5.01 MB

english, 2015

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